Part 1: A look at the impact of communication across multiple processors on an SoC and how to to make that more efficient. Managing how the processors in an SoC talk to one another is no small feat, ...

In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across ...

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, ...