Innosilicon First To Ship LPDDR6 Memory IP At Blistering 14.4Gbps Speeds

This isn't about memory chips, but implementable logic blocks for chip vendors, and it's a significant milestone for the ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
TweakTown

Rambus details HBM4 memory controller: up to 10Gb/s, 2.56TB/sec bandwidth, 64GB per stack

JEDEC is still finalizing the HBM4 memory specifications, with Rambus teasing its next-gen HBM4 memory controller that will be prepared for next-gen AI and data center markets, continuing to expand ...
CNET

Why Intel doesn't include a memory controller on its chips

Michael Kanellos is editor at large at CNET News.com, where he covers hardware, research and development, start-ups and the tech industry overseas. If you want to know why Intel doesn't include a ...