While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Cupertino, Calif. How do you design a 10-million-gate chip on a tight schedule? Not one gate at a time. Simon Bloch is president and CEO of Aristo Technology Inc., Cupertino, Calif. The recent winner ...
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