Semiconductor Engineering

Hierarchical DFT On A Flat Layout Design

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules. Hierarchical DFT divides the design into smaller pieces, creates test ...
EDN

Glossary and terms for SOC hierarchical-design

Cell library: A compilation of standard cells, hard-IP (intellectual-property) cores, and other macro blocks that comprise different functions within a library that a layout tool uses to construct a ...
Electronic Design

Synopsys Debuts DesignWare STAR Hierarchical System to Accelerate SoC Test

September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...
EDN

Cache and Memory Hierarchy Design

• Designed a generic Cache simulator module and modeled L1, L2 caches augmented with a Victim Cache. • Implemented using C++ and evaluated with SPEC address traces for gcc, perl, vortex, compress and ...