EDN

SystemVerilog Reference Verification Methodology: VMM Adoption

The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification ...
EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Design-Reuse

MIPS selects Imperas Reference Models for RISC-V Processor Verification

Oxford, United Kingdom, November 29 th, 2021 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the ...
Design-Reuse

Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Reference Verification Methodology (RVM)

Today’s consumers have come to expect more functionality from their electronic devices, provided in a smaller form factor. This has fueled the demand for integrated devices like smart phones, ...