Aug 1, 2019 · Dynamic random access memory, or DRAM, is a specific type of random access memory that allows for higher densities at a lower cost. The memory modules found in laptops and desktops use DRAM. Other types of memory like SRAM, MRAM, and Flash may be discussed in a future article.

DRAM的层级从宏观到微观大致分为，channel，rank，DRAM chip，bank，memory array，memory cell。其中，memory cell的存储对象为1或0，是最基础的存储单元；bank为最小可控制单元；rank基本相当于一个“内存条”(一个内存条内也可以存在多个rank)；channel则大致对应 …

• Our Approach: Adaptive-Latency DRAM (AL-DRAM) – Optimizes DRAM timing parameters for the common case (typical DIMM operating at low temperatures) • Analysis: Characterization of 115 DIMMs – Great potential to lower DRAM timing parameters (17 – 54%) without any errors • Real System Performance Evaluation

・Passive 1Tr1C cell leads all the features of dynamic circuits and design complexity. The row circuits is fully different from SRAM. because of both the technology saturation and the narrow band-width itself. for the coming embedded era.

Organizing Banks and Arrays • A rank is split into many banks (4-16) to boost parallelism within a rank • Ranks and banks offer memory-level parallelism • A bank is made up of multiple arrays (subarrays, tiles, mats) • To maximize density, arrays within a bank are made large rows are wide row buffers are wide (8KB read for a

•DIMM, rank, bank, array form a hierarchy in the storage organization •Because of electrical constraints, only a few DIMMs can be attached to a bus •Ranks help increase the capacity on a DIMM •Multiple DRAM chips are used for every access to improve data transfer bandwidth •Multiple banks are provided so we can be simultaneously

• A DRAM bank is a 2D array of cells: rows x columns • A “DRAM row”is also called a “DRAM page” • “Sense amplifiers”also called “row buffer”

DRAM Architecture DRAM chips are large, rectangular arrays of mem-ory cells with support logic that is used for reading and writing data in the arrays, and refresh circuitry to maintain the integrity of stored data. Memory Arrays Memory arrays are arranged in rows and columns of memory cells called wordlines and bitlines, respec-tively.

In DRAM (Dynamic Random Access Memory), a "mat" refers to a subarray or a smaller array within the larger DRAM chip. Here are some details about what a mat is and its significance in DRAM design: Definition and Structure. Mat: A mat in DRAM is a subdivision of the DRAM array.

2Gb * 8 DRAM Chips (one side of the rank) Total 16 chips + 2 chips for ECC (for both the ranks) 64 bit + 8 bit ECC interface (72 bit wide DIMM) Transferring a 64B cache line will take 8 transfers of 8B each 8B will come from 8 chips (8 bits from one chip) 1 bit from each DRAM array assuming 8 DRAM arrays per bank